1. Field of the Invention
The present invention relates to a fabrication method for a semiconductor device that has a capacitor formed on a semiconductor substrate.
2. Description of the Related Art
A semiconductor device that has a capacitor incorporated into an integrated circuit, such as DRAM (Dynamic Random Access Memory), has been known.
Recently, technology to use BaTiO.sub.3 and SrTiO.sub.3 for a dielectric film of the capacitor is being proposed.
For example, the following documents disclose such technology.
(1) S. Yamamichi et al., 1995 IEDM Technical Digest, p. 119
(2) K. P. Lee et al., 1995 IEDM Technical Digest, p. 910
(3) Japanese Laid-open Publication No. 50395/95
As above documents (1) and (2) disclose, the use of BaTiO.sub.3 and SrTiO.sub.3 for a dielectric film improves insulation performance of the dielectric film, and as a consequence, a capacitor with high dielectric constant can be fabricated for a semiconductor device with a high degree of integration. This technology is expected to be adopted for such a semiconductor device as giga bit scale large capacity DRAM.
Also, as above document (3) discloses, when two or more capacitors are formed by two or more pairs of top electrode and bottom electrode and one layer of BaTiO.sub.3 dielectric film, parasitic capacitance can be decreased by forming an area of the dielectric film, that does not contact the top electrode and the bottom electrode, to be amorphous for dropping dielectric constant.
FIG. 12 is a cross-section depicting the structure of major sections of a conventional DRAM.
FIG. 12 shows a silicon dioxide film 1202 used as a device isolation film and diffusion layers 1203a and 1203b which are part of MOS transistors on the surface of a silicon wafer 1201. On the entire surface of the wafer 1201, a layer insulation film 1204, a SiN film 1205, a layer interconnect film 1206a, for instance, made from polysilicon, and a conductive layer made from Ru, RuO.sub.2 or Pt are formed. The layer interconnect film 1206a and the conductive layer 1206b compose a bottom electrode 1206.
A dielectric film 1207 and a top electrode 1208 are laminated on the conductive layer 1206b and on the SiN film 1205. And a layer insulation film 1209 is formed on the top electrode 1208 and on the dielectric film 1207.
On the surface of the insulation film 1209, interconnect patterns 1210 and 1211 are formed. The interconnect pattern 1210 and the diffusion layer 1203b are connected with a layer interconnect film 1212, and the interconnect pattern 1211 and the top electrode 1208 are connected with a layer interconnect film 1213.
In order to form the film 1212 in the DRAM that has such structure, a contact hole that penetrates through films 1204, 1205, 1207 and 1209 must be formed.
When the dielectric film 1207 comprises of the BaTiO.sub.3 film or the SrTiO.sub.3 film, however, it is difficult to remove the dielectric film 1207 by dry etching, such as RIE (Reactive Ion Etching), therefore forming the contact hole is difficult. This is because a compound that is generated by Ba, Sr or Ti, and the etching gas component (e.g. C1) has a high melting point, that is, low volatility.
If wet etching is used instead, the dielectric film 1207 that comprises of BaTiO.sub.3 and SrTiO.sub.3 can be removed easily. However, it is difficult to use wet etching for a DRAM that has a high degree of integration, because anisotropy of wet etching is small.
The technology disclosed in above document (3), which merely alters a part of a dielectric film that comprises BaTiO.sub.3 and other components to be amorphous, can decrease the dielectric constant of parasitic capacitance, but cannot eliminate the parasitic capacitance completely. This technology still can not solve the problem that the forming of the above mentioned contact hole is difficult.
Although DRAM is used here as an example for explanation, this kind of problem always occurs to semiconductor devices that have a high degree of integration.